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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">cy_stc_scb_uart_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__scb.html">SCB          (Serial Communication Block)</a> &raquo; <a class="el" href="group__group__scb__uart.html">UART (SCB)</a> &raquo; <a class="el" href="group__group__scb__uart__data__structures.html">Data Structures</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>UART configuration structure. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ae3ffcd78ef51b5dd068bd87ef129d78e"><td class="memItemLeft" align="right" valign="top"><a id="ae3ffcd78ef51b5dd068bd87ef129d78e"></a>
<a class="el" href="group__group__scb__uart__enums.html#gaff3a50e4dbd1e0efe1550b05816e1a65">cy_en_scb_uart_mode_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#ae3ffcd78ef51b5dd068bd87ef129d78e">uartMode</a></td></tr>
<tr class="memdesc:ae3ffcd78ef51b5dd068bd87ef129d78e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies the UART's mode of operation. <br /></td></tr>
<tr class="separator:ae3ffcd78ef51b5dd068bd87ef129d78e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3174ca2a227f57bf9682c2dee729b2ff"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a3174ca2a227f57bf9682c2dee729b2ff">oversample</a></td></tr>
<tr class="memdesc:a3174ca2a227f57bf9682c2dee729b2ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Oversample factor for UART.  <a href="#a3174ca2a227f57bf9682c2dee729b2ff">More...</a><br /></td></tr>
<tr class="separator:a3174ca2a227f57bf9682c2dee729b2ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a944ceb09b14f3153bd6638c9410362e4"><td class="memItemLeft" align="right" valign="top"><a id="a944ceb09b14f3153bd6638c9410362e4"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a944ceb09b14f3153bd6638c9410362e4">dataWidth</a></td></tr>
<tr class="memdesc:a944ceb09b14f3153bd6638c9410362e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">The width of UART data (valid range is 5 to 9) <br /></td></tr>
<tr class="separator:a944ceb09b14f3153bd6638c9410362e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a318582ec552fe0bb0d19f27be93ba3a3"><td class="memItemLeft" align="right" valign="top"><a id="a318582ec552fe0bb0d19f27be93ba3a3"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a318582ec552fe0bb0d19f27be93ba3a3">enableMsbFirst</a></td></tr>
<tr class="memdesc:a318582ec552fe0bb0d19f27be93ba3a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the hardware to shift out data element MSB first; otherwise, LSB first. <br /></td></tr>
<tr class="separator:a318582ec552fe0bb0d19f27be93ba3a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a621fdf75f6e9856d92bdbf1da793f2b9"><td class="memItemLeft" align="right" valign="top"><a id="a621fdf75f6e9856d92bdbf1da793f2b9"></a>
<a class="el" href="group__group__scb__uart__enums.html#ga980f6c273a50db8f6b6fa7f703b1a7f9">cy_en_scb_uart_stop_bits_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a621fdf75f6e9856d92bdbf1da793f2b9">stopBits</a></td></tr>
<tr class="memdesc:a621fdf75f6e9856d92bdbf1da793f2b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies the number of stop bits in the UART transaction, in half-bit increments. <br /></td></tr>
<tr class="separator:a621fdf75f6e9856d92bdbf1da793f2b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8105fe188535ea1d434fcf4449f8f3f5"><td class="memItemLeft" align="right" valign="top"><a id="a8105fe188535ea1d434fcf4449f8f3f5"></a>
<a class="el" href="group__group__scb__uart__enums.html#ga5ee6d587ef3399954d609f17775a3f42">cy_en_scb_uart_parity_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a8105fe188535ea1d434fcf4449f8f3f5">parity</a></td></tr>
<tr class="memdesc:a8105fe188535ea1d434fcf4449f8f3f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the UART parity. <br /></td></tr>
<tr class="separator:a8105fe188535ea1d434fcf4449f8f3f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a11ed4ced763dc661cf7e3b5456ec6157"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a11ed4ced763dc661cf7e3b5456ec6157">enableInputFilter</a></td></tr>
<tr class="memdesc:a11ed4ced763dc661cf7e3b5456ec6157"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables a digital 3-tap median filter (2 out of 3 voting) to be applied to the input of the RX FIFO to filter glitches on the line (for IrDA, this parameter is ignored)  <a href="#a11ed4ced763dc661cf7e3b5456ec6157">More...</a><br /></td></tr>
<tr class="separator:a11ed4ced763dc661cf7e3b5456ec6157"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3d815bb37e49de4d14869223229f8f54"><td class="memItemLeft" align="right" valign="top"><a id="a3d815bb37e49de4d14869223229f8f54"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a3d815bb37e49de4d14869223229f8f54">dropOnParityError</a></td></tr>
<tr class="memdesc:a3d815bb37e49de4d14869223229f8f54"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the hardware to drop data in the RX FIFO when a parity error is detected. <br /></td></tr>
<tr class="separator:a3d815bb37e49de4d14869223229f8f54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9601c46e2d7125724893590bc88f38c2"><td class="memItemLeft" align="right" valign="top"><a id="a9601c46e2d7125724893590bc88f38c2"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a9601c46e2d7125724893590bc88f38c2">dropOnFrameError</a></td></tr>
<tr class="memdesc:a9601c46e2d7125724893590bc88f38c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the hardware to drop data in the RX FIFO when a frame error is detected. <br /></td></tr>
<tr class="separator:a9601c46e2d7125724893590bc88f38c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7c7ac1a64405b9351d1f011520795e7e"><td class="memItemLeft" align="right" valign="top"><a id="a7c7ac1a64405b9351d1f011520795e7e"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a7c7ac1a64405b9351d1f011520795e7e">enableMutliProcessorMode</a></td></tr>
<tr class="memdesc:a7c7ac1a64405b9351d1f011520795e7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the UART operation in Multi-Processor mode which requires dataWidth to be 9 bits (the 9th bit is used to indicate address byte) <br /></td></tr>
<tr class="separator:a7c7ac1a64405b9351d1f011520795e7e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae9c4c69d7c329e66c3fd1bd8dd3dfd52"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#ae9c4c69d7c329e66c3fd1bd8dd3dfd52">receiverAddress</a></td></tr>
<tr class="memdesc:ae9c4c69d7c329e66c3fd1bd8dd3dfd52"><td class="mdescLeft">&#160;</td><td class="mdescRight">If Multi Processor mode is enabled, this is the address of the RX FIFO.  <a href="#ae9c4c69d7c329e66c3fd1bd8dd3dfd52">More...</a><br /></td></tr>
<tr class="separator:ae9c4c69d7c329e66c3fd1bd8dd3dfd52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f28caab84a610803f57ac8514cc1ead"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a3f28caab84a610803f57ac8514cc1ead">receiverAddressMask</a></td></tr>
<tr class="memdesc:a3f28caab84a610803f57ac8514cc1ead"><td class="mdescLeft">&#160;</td><td class="mdescRight">This is the address mask for the Multi Processor address.  <a href="#a3f28caab84a610803f57ac8514cc1ead">More...</a><br /></td></tr>
<tr class="separator:a3f28caab84a610803f57ac8514cc1ead"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74ad4d501763b438b7903fb04e9df1b1"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a74ad4d501763b438b7903fb04e9df1b1">acceptAddrInFifo</a></td></tr>
<tr class="memdesc:a74ad4d501763b438b7903fb04e9df1b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the hardware to accept the matching address in the RX FIFO.  <a href="#a74ad4d501763b438b7903fb04e9df1b1">More...</a><br /></td></tr>
<tr class="separator:a74ad4d501763b438b7903fb04e9df1b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1c4cd968ea7897497e93dcb2ae3ad39c"><td class="memItemLeft" align="right" valign="top"><a id="a1c4cd968ea7897497e93dcb2ae3ad39c"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a1c4cd968ea7897497e93dcb2ae3ad39c">irdaInvertRx</a></td></tr>
<tr class="memdesc:a1c4cd968ea7897497e93dcb2ae3ad39c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Inverts the IrDA RX input. <br /></td></tr>
<tr class="separator:a1c4cd968ea7897497e93dcb2ae3ad39c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f927424c73f317022e884169583e65d"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a2f927424c73f317022e884169583e65d">irdaEnableLowPowerReceiver</a></td></tr>
<tr class="memdesc:a2f927424c73f317022e884169583e65d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the low-power receive for IrDA mode.  <a href="#a2f927424c73f317022e884169583e65d">More...</a><br /></td></tr>
<tr class="separator:a2f927424c73f317022e884169583e65d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a09c9696d4f75ebfe55d7974264a62d3d"><td class="memItemLeft" align="right" valign="top"><a id="a09c9696d4f75ebfe55d7974264a62d3d"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a09c9696d4f75ebfe55d7974264a62d3d">smartCardRetryOnNack</a></td></tr>
<tr class="memdesc:a09c9696d4f75ebfe55d7974264a62d3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables retransmission of the frame placed in the TX FIFO when NACK is received in SmartCard mode (for Standard and IrDA , this parameter is ignored) <br /></td></tr>
<tr class="separator:a09c9696d4f75ebfe55d7974264a62d3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a23f93e077ac4de987f18193e18f7944c"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a23f93e077ac4de987f18193e18f7944c">enableCts</a></td></tr>
<tr class="memdesc:a23f93e077ac4de987f18193e18f7944c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the usage of the CTS input signal for the transmitter.  <a href="#a23f93e077ac4de987f18193e18f7944c">More...</a><br /></td></tr>
<tr class="separator:a23f93e077ac4de987f18193e18f7944c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9e3b74f87a756eec81dbbba110214619"><td class="memItemLeft" align="right" valign="top"><a id="a9e3b74f87a756eec81dbbba110214619"></a>
<a class="el" href="group__group__scb__uart__enums.html#gadd7a3cc34b487e9898095db7b1638098">cy_en_scb_uart_polarity_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a9e3b74f87a756eec81dbbba110214619">ctsPolarity</a></td></tr>
<tr class="memdesc:a9e3b74f87a756eec81dbbba110214619"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the CTS Polarity. <br /></td></tr>
<tr class="separator:a9e3b74f87a756eec81dbbba110214619"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04b3320e809245b5b6736a4dbba1e9cd"><td class="memItemLeft" align="right" valign="top"><a id="a04b3320e809245b5b6736a4dbba1e9cd"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a04b3320e809245b5b6736a4dbba1e9cd">rtsRxFifoLevel</a></td></tr>
<tr class="memdesc:a04b3320e809245b5b6736a4dbba1e9cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">When the RX FIFO has fewer entries than rtsRxFifoLevel, the RTS signal is active (note to disable RTS, set this field to zero) <br /></td></tr>
<tr class="separator:a04b3320e809245b5b6736a4dbba1e9cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aef45f44278f9c550d9b0be95e505bd3e"><td class="memItemLeft" align="right" valign="top"><a id="aef45f44278f9c550d9b0be95e505bd3e"></a>
<a class="el" href="group__group__scb__uart__enums.html#gadd7a3cc34b487e9898095db7b1638098">cy_en_scb_uart_polarity_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#aef45f44278f9c550d9b0be95e505bd3e">rtsPolarity</a></td></tr>
<tr class="memdesc:aef45f44278f9c550d9b0be95e505bd3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the RTS Polarity. <br /></td></tr>
<tr class="separator:aef45f44278f9c550d9b0be95e505bd3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a923970897f4434aadda6bee185a2367d"><td class="memItemLeft" align="right" valign="top"><a id="a923970897f4434aadda6bee185a2367d"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a923970897f4434aadda6bee185a2367d">breakWidth</a></td></tr>
<tr class="memdesc:a923970897f4434aadda6bee185a2367d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies the number of bits to detect a break condition. <br /></td></tr>
<tr class="separator:a923970897f4434aadda6bee185a2367d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abca36ee02b4004875fdb71f271de6e1b"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#abca36ee02b4004875fdb71f271de6e1b">breaklevel</a></td></tr>
<tr class="memdesc:abca36ee02b4004875fdb71f271de6e1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies the low or high level pulse detection for break condition.  <a href="#abca36ee02b4004875fdb71f271de6e1b">More...</a><br /></td></tr>
<tr class="separator:abca36ee02b4004875fdb71f271de6e1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a597786d939a3002a980e150cb65c8311"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a597786d939a3002a980e150cb65c8311">rxFifoTriggerLevel</a></td></tr>
<tr class="memdesc:a597786d939a3002a980e150cb65c8311"><td class="mdescLeft">&#160;</td><td class="mdescRight">When there are more entries in the RX FIFO than this level the RX trigger output goes high.  <a href="#a597786d939a3002a980e150cb65c8311">More...</a><br /></td></tr>
<tr class="separator:a597786d939a3002a980e150cb65c8311"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2ad10b825a71d9ba1b6bb1a576c4ae11"><td class="memItemLeft" align="right" valign="top"><a id="a2ad10b825a71d9ba1b6bb1a576c4ae11"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a2ad10b825a71d9ba1b6bb1a576c4ae11">rxFifoIntEnableMask</a></td></tr>
<tr class="memdesc:a2ad10b825a71d9ba1b6bb1a576c4ae11"><td class="mdescLeft">&#160;</td><td class="mdescRight">The bits set in this mask allow the event to cause an interrupt (See <a class="el" href="group__group__scb__uart__macros__rx__fifo__status.html">UART RX FIFO status.</a> for the set of constants) <br /></td></tr>
<tr class="separator:a2ad10b825a71d9ba1b6bb1a576c4ae11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2a061c925fe7610533730fa206d7d9c2"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#a2a061c925fe7610533730fa206d7d9c2">txFifoTriggerLevel</a></td></tr>
<tr class="memdesc:a2a061c925fe7610533730fa206d7d9c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">When there are fewer entries in the TX FIFO then this level the TX trigger output goes high.  <a href="#a2a061c925fe7610533730fa206d7d9c2">More...</a><br /></td></tr>
<tr class="separator:a2a061c925fe7610533730fa206d7d9c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae26c57833e5fc79caab39ba246a5e373"><td class="memItemLeft" align="right" valign="top"><a id="ae26c57833e5fc79caab39ba246a5e373"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__scb__uart__config__t.html#ae26c57833e5fc79caab39ba246a5e373">txFifoIntEnableMask</a></td></tr>
<tr class="memdesc:ae26c57833e5fc79caab39ba246a5e373"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bits set in this mask allows the event to cause an interrupt (See <a class="el" href="group__group__scb__uart__macros__tx__fifo__status.html">UART TX FIFO Statuses</a> for the set of constants) <br /></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#a3174ca2a227f57bf9682c2dee729b2ff">&#9670;&nbsp;</a></span>oversample</h2>

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<p>Oversample factor for UART. </p>
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<li>The UART baud rate is the SCB Clock frequency / oversample (valid range is 8-16).</li>
<li>For IrDA, the oversample is always 16, unless <a class="el" href="structcy__stc__scb__uart__config__t.html#a2f927424c73f317022e884169583e65d">irdaEnableLowPowerReceiver</a> is enabled. Then the oversample is reduced to the <a class="el" href="group__group__scb__uart__macros__irda__lp__ovs.html">UART IRDA Low Power Oversample factors</a> set. </li>
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<h2 class="memtitle"><span class="permalink"><a href="#a11ed4ced763dc661cf7e3b5456ec6157">&#9670;&nbsp;</a></span>enableInputFilter</h2>

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<p>Enables a digital 3-tap median filter (2 out of 3 voting) to be applied to the input of the RX FIFO to filter glitches on the line (for IrDA, this parameter is ignored) </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae9c4c69d7c329e66c3fd1bd8dd3dfd52">&#9670;&nbsp;</a></span>receiverAddress</h2>

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<p>If Multi Processor mode is enabled, this is the address of the RX FIFO. </p>
<p>If the address matches, data is accepted into the FIFO. If it does not match, the data is ignored. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a3f28caab84a610803f57ac8514cc1ead">&#9670;&nbsp;</a></span>receiverAddressMask</h2>

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<p>This is the address mask for the Multi Processor address. </p>
<p>1 indicates that the incoming address must match the corresponding bit in the slave address. A 0 in the mask indicates that the incoming address does not need to match. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a74ad4d501763b438b7903fb04e9df1b1">&#9670;&nbsp;</a></span>acceptAddrInFifo</h2>

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<p>Enables the hardware to accept the matching address in the RX FIFO. </p>
<p>This is useful when the device supports more than one address. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2f927424c73f317022e884169583e65d">&#9670;&nbsp;</a></span>irdaEnableLowPowerReceiver</h2>

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<p>Enables the low-power receive for IrDA mode. </p>
<p>Note that the transmission must be disabled if this mode is enabled. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a23f93e077ac4de987f18193e18f7944c">&#9670;&nbsp;</a></span>enableCts</h2>

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<p>Enables the usage of the CTS input signal for the transmitter. </p>
<p>The transmitter waits for CTS to be active before sending data </p>

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<h2 class="memtitle"><span class="permalink"><a href="#abca36ee02b4004875fdb71f271de6e1b">&#9670;&nbsp;</a></span>breaklevel</h2>

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<p>Specifies the low or high level pulse detection for break condition. </p>
<dl class="section note"><dt>Note</dt><dd>This parameter is available for CAT1B, CAT1C and CAT1D devices. </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#a597786d939a3002a980e150cb65c8311">&#9670;&nbsp;</a></span>rxFifoTriggerLevel</h2>

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<p>When there are more entries in the RX FIFO than this level the RX trigger output goes high. </p>
<p>This output can be connected to a DMA channel through a trigger mux. Also, it controls the <a class="el" href="group__group__scb__uart__macros__rx__fifo__status.html#ga2c2ad72882685c29a4755ead9e5bcda9">CY_SCB_UART_RX_TRIGGER</a> interrupt source. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a2a061c925fe7610533730fa206d7d9c2">&#9670;&nbsp;</a></span>txFifoTriggerLevel</h2>

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<p>When there are fewer entries in the TX FIFO then this level the TX trigger output goes high. </p>
<p>This output can be connected to a DMA channel through a trigger mux. Also, it controls <a class="el" href="group__group__scb__uart__macros__tx__fifo__status.html#ga084f44adc0f1fba7bc8cc63f46c8a3e6">CY_SCB_UART_TX_TRIGGER</a> interrupt source. </p>

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